1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to an apparatus and method for increasing cell capacitance in a static random access memory cell.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today's high-speed computer systems, the relative size of electronic devices is steadily decreasing while system performance is steadily increasing. Thus, higher performance systems are being designed to consume less space. Accordingly, the electronic components that make up computer systems, such as processors, memory devices, or other peripherals are being designed to occupy less space. For example, memory devices, such as static random access devices (SRAMs), are being fabricated with decreased memory cell size.
As the SRAM's cell size decreases, the associated capacitance of the SRAM cell decreases as well. The critical charge of the SRAM cell is proportional to the capacitance of the cell. Disadvantageously, the decrease in parasitic capacitance in the SRAM cell makes it more susceptible to potential problems, such as soft error failure. Soft error failure is caused when a radioactive particle, such as an alpha particle, hits a junction area in an SRAM cell thereby creating free charges. If the charges created are greater than the critical charge of the SRAM cell, then the information stored in the cell may be lost because the data is corrupted. Depending on the specific information that is stored in the SRAM cells, these errors may impact the system's performance.
One method that is often used to combat soft error failures is to add capacitor plates on top of the SRAM cell to add extra capacitance. Disadvantageously, in adding plates to the top of the SRAM cell, additional photolithography steps may be required to fabricate the additional structure. This increases the time to fabricate the SRAM cells and increases the overall cost of the fabrication process.